We use techniques from just in time compilers to accelerate Verilog processor simulations. Our simulator outperforms existing simulators by up to 100x on the same hardware, while retaining cycle-accuracy. Have a look at our demo video to see it in action!
Contact us!
We are opening conversations with processor design teams and investors. If you you are interested in blazingly fast RTL simulations, please reach out to us!
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About us
Can Joshua Lehmann is a software developer with a background in compilers and hardware design. He has designed and implemented verijit's JIT compiler and is responsible for the overall architecture of the project.